The invention relates to an improvement in semiconductor memory cell device, and more particularly to an improvement in a high density stacked capacitor dynamic random access memory (DRAM) cell device.
In recent years, an improvement in a high integration of a semiconductor memory cell device such as a stacked capacitor dynamic random access memory cell device is required. Actually, whether a considerable improvement in the high integration of the semiconductor memory cell device is achievable depends upon fine pattern technologies. The realization of the high density semiconductor memory cell device, thus, depends upon how much scale down or high fine pattern of the device is accomplished. One of the most important factors concerned with the fine pattern technologies is the accuracy of patterning of the photo-lithography. Achievement of a possible improvement in the accuracy of patterning of the photo-lithography is important for accomplishment of the scaling down of the device. In addition, it is also important to secure a high reliability of the high density semiconducutor memory cell device.
With respect to the fine structure of the device, 3-dimensional stacked capacitor cells for the dynamic random access memory device (DRAM) have been proposed to secure both the high density and the high reliability. The 3-dimensional stacked capacitor cell structure permits the stacked capacitor to have a relatively large capacitance with a relatively small area. The 3-dimensional stacked capacitor cell for the dynamic random access memory device (DRAM) has a high density. This is why the 3-dimensional stacked capacitor cell structure is attractive as one of the high density capacitor cell structures in replacement of the conventional cell plate structure for the dynamic random access memory device (DRAM).
Such 3-dimensional stacked capacitor cell for the dynamic random access memory device (DRAM) is, however, engaged with a disadvantage in a restriction on the improvement in the scaling down or the fine structure of the device. As described above, the accuracy of the patterning of the photo-lithography provides the restriction on the improvement in the scaling down or the fine structure of the device. It is important for implementation of the scaling down or the fine structure of the device to realize a possible high accuracy of the patterning of the photo-lithography. One of the important factors which define the accuracy of the patterning of the photo-lithography is the degree of the flatness of a device surface to be exposed to an ultra-violet ray for photo-etching in the photo-lithography process.
In general, when the leveling of the device surface to be exposed to the ultra-violet ray for the photo-etching of the photo-lithography is inferior, the accuracy of the patterning of the photo-lithography is also inferior. It is, thus, difficult to obtain a fine pattern of the device by the photo-etching of the present photo-lithography techniques. This results in the difficulty in implementation of the scaling down of the device. This makes it difficult to improve the high integration of the 3-dimensional stacked capacitor memory cell device.
In contrast, when the leveling of the device surface to be exposed to the ultra-violet ray for the photo-etching of the photo-lithography is superior, the accuracy of the patterning of the photo-lithography is also superior. It is thus possible to obtain a fine pattern of the device by the photo-etching of the present photo-lithography techniques. This results in the implementation of the scaling down of the device. From the above description, the following matters will be apparent.
The realization of the scaling down and thus the high accuracy of the patterning of the photo-lithography depends upon how much effective and sufficient leveling of the device surface to be subjected to the photo-lithography is achievable. Physically, it is, however, difficult to realize the complete leveling of the device surface. Particularly, in case of the 3-dimensional stacked capacitor cell for the dynamic random access memory device (DRAM), the difficulty in accomplishment of the complete leveling of the device surface is considerable. The causes of the difficulty in accomplishment of the leveling of the device surface to be exposed to the photo-lithography will be described. The 3-dimensional stacked capacitor cell dynamic random access memory device (DRAM) includes a memory cell array area and a peripheral circuit area which encompasses the memory cell array area. The memory cell array area includes stacked capacitors and switching transistors. The peripheral circuit area includes sense amplifiers and decoders and the like. Both the memory cell array area and the peripheral circuit area have a difference in the density of elements formed therein. Further, both the memory cell array area and the peripheral circuit area also have a difference in the level at a boundary area thereof. Such differences in the density and level which appear the boundary area between the memory cell array area and the peripheral circuit area provide an inferiority to the accuracy of the patterning of the photo-lithography at the boundary area between the memory cell array area and the peripheral circuit area. This further provides undesirable affections to the circuit performances of the 3-dimensional stacked capacitor cell dynamic random access memory device (DRAM). Such inferior accuracy of the patterning of the photo-lithography makes it difficult to improve the scaling down and the fine pattern of the device.
To combat the above problem in the leveling, it has been proposed to make adjacent memory cells to the boundary area serves as dummy memory cells. As described above, the inferiority in the accuracy of the patterning of the photo-lithography appears at the boundary area exhibiting the difference in the level between the memory cell array area and the peripheral circuit area. In this case even if there exists a relatively large difference in the level at the boundary area between the memory cell array area and the peripheral circuit area, only the dummy memory cells adjacent to the boundary area are subjected to undesirable affections of the inferiority in the accuracy of the patterning of the photo-lithography. This makes other operative memory cells free from such undesirable affections of the inferiority in the accuracy of the pattern of the photo-lithography. Even if the inferiority in the accuracy of the pattern of the photo-lithography appears in the dummy memory cell area, no inferiority in the accuracy of the pattern of the photo-lithography appears in the operational memory cell array area.
However, such 3-dimensional stacked capacitor memory cell device also has the following problem in the inferiority in the accuracy of the pattern of the photo-lithography. Such 3-dimensional stacked capacitor memory cell array includes a plurality of digit lines which lay not only in both the memory cell array area and the peripheral circuit area but also in the boundary area exhibiting the level difference. Thus, the problem in the inferiority in the accuracy of the pattern of the photo-lithography appears on the digit lines at the boundary area exhibiting the level difference.
The above mentioned matters concerned with the restriction on the scaling down and thus the fine pattern structure in the photo-lithography techniques will be more clear from the following description of one example of the 3-dimensional stacked capacitor cell structures for the dynamic random access memory device. FIGS. 1A and 1B are respectively plan and cross sectional elevation views which illustrate the structure of the conventional 3-dimensional stacked capacitor cell for the dynamic random access memory device.
The conventional 3-dimensional stacked capacitor cell for the dynamic random access memory device has a p-type silicon substrate 1. Field oxide films 11 are formed in a surface of the p-type silicon substrate 1 so that an active region is defined. Diffusion layers 3-1 and 3-2 are selectively formed in the active region of the surface of the p-type silicon substrate 1 whereby a channel region is defined between the n-type diffusion layers 3-1 and 3-2. The n-type diffusion layers 3-1 and 3-2 serve as source and drain regions of a switching transistor. A word line 4 is formed over the channel region of the switching transistor through an insulator film. The word line 4 serves as a gate electrode in the switching transistor region. The switching transistor in the memory cell comprises the source and drain regions of the n-type diffusion layers 3-1 and 3-2 and the gate electrode of the word-line 4.
An insulation film 12 is formed on the switching transistor region and the field oxide film 11. A contact hole C1 is formed in the insulator film 12 over one of the n-type diffusion layers 3-1 and 3-2 serving as the source and drain regions. A first capacitor electrode 6 is so formed as to contact through the contact hole C1 to the one of the n-type diffusion layers 3-1 and 3-2 serving as the source and drain diffusion layers. A capacitor insulation film 7 is so formed as to cover the first capacitor electrode 6. A second capacitor electrode 8 is formed on the capacitor insulation film 7 so that the stacked capacitor is formed. The stacked capacitor comprises the first and second capacitor electrodes 6 and 8 and the capacitor insulation film 7. The memory cell comprises the stacked capacitor and the switching transistor.
A first inter-layer insulator 13 is formed on the stacked capacitor and the insulation film 12. A digit line 10 is formed on the first inter-layer insulator 13. A second inter-layer insulator 14 is formed on the digit line 10. The digit line 10 serves to transmit digit signals. However, the digit line 10 is not electrically connected to another of the n-type diffusion layers 3-1 and 3-2 serving as the source and drain regions so as to make the memory cell comprising the stacked capacitor and the switching transistor becomes the dummy memory cell. Namely, the disconnection between the switching transistor and the digit line 10 does not allow the digit signals to be transmitted from the digit line 10 to the stacked capacitor through the switching transistor, even if the switching transistor takes ON state. This is why the memory cell serves as a dummy memory cell.
The dummy memory cells exists at the adjacent portions to the boundary area exhibiting a level difference H3 between the memory cell array area and the peripheral circuit area. The dummy memory cells are subjected to undesirable affections caused by the inferiority in the accuracy of the pattern of the photo-lithography in replacement of the operational memory cells. Namely, the undesirable affection in the inferiority in the accuracy of the pattern of the photo-lithography is caused by the level difference H3 existing at the boundary area between the memory cell array area and the peripheral circuit area. Even if the dummy memory cells adjacent to the boundary area suffer the affection of the inferiority in the accuracy of the pattern of the photo-lithography, no problem in the inferior accuracy of the pattern of the photo-lithography occurs in the operational memory cell array area.
As described above, the digit line 10, however, lays in not only both the memory cell array area and the peripheral circuit area but also the boundary area exhibiting the level difference H3 which causes the inferiority in the accuracy of the pattern of the photo-lithography. This is why the digit line 10 is engaged with the problem in appearance of the inferiority of the accuracy of the pattern of the photo-lithography at the boundary area expressing the level difference H3. As the level difference is large, the inferiority in the accuracy of the pattern of the photo-lithography is considerable. Since the 3-dimensional stacked capacitor memory cell array has the relatively large difference H3 in the level, the inferiority in the accuracy of the pattern of the photo-lithography is considerable. Such inferior accuracy of the pattern makes it difficult for the 3-dimensional stacked capacitor memory cell array device to obtain a fine pattern. This provides a restriction on the scaling down of the device.
The caution of the above mentioned problem with the digit line 10 is in the level difference H3 appearing at the boundary area between the memory cell array area and the peripheral circuit area. If there exists no large difference in the level at the boundary area between the memory cell array area and the peripheral circuit area, the digit line 10 is free from the problem in the inferiority in the accuracy of the pattern of the photo-lithography which provides the restriction on accomplishments of the scaling down and the fine pattern structure of the device. Such restriction on the accomplishments of the scaling down and the fine pattern structure of the device makes the improvement in the high high integration or the high density of the memory cell device difficult.
It is, therefore, required for overcoming the above problem to realize such effective and sufficient leveling of the device surface particularly the digit lines 10 that the inferiority in the accuracy of the pattern of the photo-lithography does not appear at the boundary area between the memory cell array area and the peripheral circuit area.